Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /I2C0 /I2C_RAW_INTR_STAT

Set if the processor attempts to read the receive buffer when it is empty by reading from the I2C_DATA_CMD register. If the module is disabled(I2C_ENABLE[ENABLE] is set ot 0x0), this bit keeps its level until the master or slave state machines go into IDLE, and when I2C_ENABLE[ENABLE] is set ot 0x0, this interrupt is cleared.

0 (Val_0x0): RX_UNDER interrupt is inactive

1 (Val_0x1): RX_UNDER interrupt is active

Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[ENABLE] is set ot 0x0), this bit keeps its level until the master or slave state machines go into IDLE, and when I2C_ENABLE[ENABLE] is set ot 0x0, this interrupt is cleared.

0 (Val_0x0): RX_OVER interrupt is inactive

1 (Val_0x1): RX_OVER interrupt is active

Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[ENABLE] is set to 0x0), the Rx FIFO is flushed and held in reset; therefore the Rx FIFO is not full. So, this bit is cleared once the I2C_ENABLE[ENABLE] bit is set to 0x0, regardless of the activity that continues.

0 (Val_0x0): RX_FULL interrupt is inactive

1 (Val_0x1): RX_FULL interrupt is active

Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the I2C_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into IDLE, and when I2C_ENABLE[ENABLE] goes to 0x0, this interrupt is cleared.

0 (Val_0x0): TX_OVER interrupt is inactive

1 (Val_0x1): TX_OVER interrupt is active

The behavior of the TX_EMPTY interrupt status differs based on the selection in the I2C_CON[TX_EMPTY_CTRL] bit. When TX_EMPTY_CTRL is set to 0x0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. When TX_EMPTY_CTRL is set to 0x1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed.

0 (Val_0x0): TX_EMPTY interrupt is inactive

1 (Val_0x1): TX_EMPTY interrupt is active

This bit is set to 0x1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write there quested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register.

0 (Val_0x0): RD_REQ interrupt is inactive

1 (Val_0x1): RD_REQ interrupt is active

This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of theTx FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort. When this bit is set to 0x1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the I2C_TX_ABRT_SOURCE register. The Tx FIFO remains in this flushed state until the I2C_CLR_TX_ABRT register is read. Once this read is performed, theTx FIFO is then ready to accept more data bytes from the APB interface.

0 (Val_0x0): TX_ABRT interrupt is inactive

1 (Val_0x1): TX_ABRT interrupt is active

When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.

0 (Val_0x0): RX_DONE interrupt is inactive

1 (Val_0x1): RX_DONE interrupt is active

This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it:

• Disabling the I2C
• Reading the I2C_CLR_ACTIVITY register
• Reading the I2C_CLR_INTR register
• System reset

0 (Val_0x0): RAW_INTR_ACTIVITY interrupt is inactive

1 (Val_0x1): RAW_INTR_ACTIVITY interrupt is active

Indicates whether a STOP condition has occurred on the I^2C interface regardless of whether I2C is operating in Slave or Master mode. In Slave mode: If I2C_CON[STOP_DET_IFADDRESSED] is set to 0x1 , the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if I2C_CON[STOP_DET_IFADDRESSED] is set to 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). If I2C_CON[STOP_DET_IFADDRESSED] is set to 0x0, the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master mode: If I2C_CON[STOP_DET_IF_MASTER_ACTIVE] is set to 0x1, the STOP_DET interrupt will be issued only if master is active. If I2C_CON[STOP_DET_IF_MASTER_ACTIVE] is set to 0x0, the STOP_DET interrupt will be issued irrespective of whether master is active or not.

0 (Val_0x0): STOP_DET interrupt is inactive

1 (Val_0x1): STOP_DET interrupt is active

Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in Slave or Master mode.

0 (Val_0x0): START_DET interrupt is inactive

1 (Val_0x1): START_DET interrupt is active

Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C stores the received data in the Rx buffer.

0 (Val_0x0): GEN_CALL interrupt is inactive

1 (Val_0x1): GEN_CALL interrupt is active

Indicates whether a RESTART condition has occurred on the I^2C interface when I2C is operating in Slave mode and the slave is being addressed. During a Start Byte transfer, the RESTART comes before the address field as per the I^2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt.

0 (Val_0x0): RESTART_DET interrupt is inactive

1 (Val_0x1): RESTART_DET interrupt is active

Indicates whether master is holding the bus and TX FIFO is empty.

0 (Val_0x0): MASTER_ON_HOLD interrupt is inactive

1 (Val_0x1): MASTER_ON_HOLD interrupt is active

Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of IC_CLK periods.

0 (Val_0x0): SCL_STUCK_AT_LOW interrupt is inactive

1 (Val_0x1): SCL_STUCK_AT_LOW interrupt is active